As the amount of data to be transferred by way of networks rises, the need of realizing high speed data communication networks at low cost has been intensified to common carriers for telecommunications. A shift from high cost networks employing a time division multiplexing (TDM) system to low cost and high efficiency networks employing an Internet protocol system (to be referred to as “IP system” hereinafter) is on the way.
Accurate clock synchronization is required to some traffics of data being transferred on networks both at the sending node side and at the receiving node side. For example, in order to exchange high quality data including audio and video data on a real time basis, the data needs to be reproduced at predetermined timings. Stable clock synchronization is required for this purpose.
In the case of mobile network services, again for example, accurate clock synchronization is required to realize handovers between cells without delay. More specifically, a very high clock synchronization accuracy of 50 [ppb: parts per billion] is required to each base station device on a mobile network relative to a radio network controller. If the clock synchronization accuracy of the base station device falls short of the required level of 50 [ppb], the inter-cell handover may fail and some data may become missing to degrade the communication quality.
In this regard, a receiving node can extract the clock information of the corresponding sending node via the transmission path in the case of networks based on a TDM system and hence it is possible to realize a high accuracy clock synchronization between the sending and receiving nodes. On the other hand, in the case of IP networks based on an IP system, data are transferred asynchronously in the network so that fluctuations of time intervals take place to data arrivals at a receiving node. Therefore, it is difficult to extract high accuracy clock information from the received data. Hence, the receiving node needs to reproduce the clock of the sending side.
Time stamp systems have been proposed as a technique of realizing a high accuracy clock reproduction via a packet network such as an IP network, which is described above. The arrangement of a time stamp system will be described below by referring to FIG. 1.
Referring to FIG. 1, master node 100 and slave node 110 are connected to each other via a packet network 130. With the time stamp system, a master node 100, which operates as a sending node, transmits a TS packet that stores a time stamp (to be referred to as “TS” hereinafter) to a slave node 110, which operates as a receiving node.
The TS packet arrives at the slave node 110 by way of the packet network 130 (see the upper part in FIG. 1). Upon receiving the TS packet, the slave node 110 adjusts its own clock, utilizing the TS information stored in the TS packet, so as to synchronize it with the clock of the master node 100. Now, the operation of clock synchronization will be described in greater detail below by explaining the configuration of the slave node 110, referring to the lower part of FIG. 1.
The slave node 110 has a phase-locked loop (PPL) (to be referred to as “PPL” hereinafter and also in the drawings) and realizes clock synchronization by computing the difference between the TS generated by its own clock and the TS received from the master node 100 and adjusting its own clock according to the difference by means of the PLL 140.
The PLL 140 has five functions including a phase comparator 141, a loop filter (LPF: low pass filter) 142, a proportion/integration (PI) circuit (to be referred to as “PI controller” hereinafter and also in the drawings) 143, a voltage controlled oscillator (VCO) 144 and a counter 145.
The phase comparator 141 computes the difference between the received TS and the TS generated by its own clock. The difference signal is then input to the LPF 142, where jitter and noise are removed from it. The difference signal smoothed by the LPF 142 is input to the PI controller 143. The PI controller 143 computes a control signal for ultimately converging the difference signal to nil and outputs it to the VCO 144. The VCO 144 outputs a clock of the frequency that is determined by the control signal from the PI controller 143 so that the slave side clock is adjusted by it. Additionally, the counter 145 generates a slave side TS on the basis of the adjusted clock and delivers it to the phase comparator 141.
Thus, it is possible for the slave node 110 to reproduce the clock of the master node 100 and synchronizes itself with the master node 100 by means of an operation of the PLL 140 as described above even by way of a packet network 130 (see, for example, PTL 1).